Ultra-wide band (20 MHz to 5 GHz) analog to digital signal processor

ABSTRACT

An ultra-wide band general purpose analog to digital signal processor ( 200 ) covering the radio frequency range from 20 MHz to 5 GHz. The processor ( 200 ) includes a first circuit for shifting a frequency of an input signal, a second circuit for processing the input signal, and a third circuit for selectively bypassing the first circuit whereby the input signal is provided directly to the second circuit in a first mode of operation and to the second circuit via the first circuit in a second mode of operation. In the illustrative embodiment, the first circuit is a mixer ( 12 ) with a normalized mixing ratio of 0.8 to 0.9. The second circuit is a sigma-delta analog-to-digital converter ( 14 ). The third circuit is a switch ( 10 ) for passing the input signal directly to the second circuit if the input is 20 MHz to 2 GHz, or for passing the input signal to the first-circuit if the input is 2 GHz to 5 GHz. In the preferred embodiment, the switch ( 10 ), the mixer ( 12 ), and the sigma-delta converter ( 14 ) are disposed on a single application specific integrated circuit (ASIC) substrate ( 100 ).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to electronic circuits and systems. Morespecifically, the present invention relates to analog to digital signalprocessors for use in communications receivers and radars.

2. Description of the Related Art

Radio frequency receivers should process the input signal as quickly aspossible, i.e. as close to the antenna as possible, in order to obtain ahigh signal to noise ratio. Receivers generally have several stages ofdown-conversion, converting the RF (radio frequency) input signal tolower intermediate frequencies (IFs). The circuitry used to down-convertthe signal, however, is subject to a number of limitations, includingnoise, drift, and dynamic range issues. It is therefore desirable toconvert the signal to digital as close as possible to the antenna.

Currently, however, digital signal processing cannot be performed at thehigh (RF) frequencies received by the antenna. Digital signal processingis usually performed after several stages of down-conversion, at lowerIFs (baseband to 100 MHz).

A digital signal processor is needed which can process the signalwithout as many intermediate stages of down-conversion, preferably atthe first IF stage. In a typical radar system, for example, the first IFstage is upwards of 5 GHz. Currently, sigma-delta analog to digitalconverters can be used to process frequencies up to only 2 GHz.Sigma-delta converters higher than 2 GHz are not possible usingcurrently available technology. Furthermore, these sigma-deltaconverters are conventionally narrow-band frequency specific integratedcircuits with internally tuned electrical elements, such that differentsigma-delta converters would need to be produced for use at differentfrequencies, dictating specific individual devices for each application.It would be more cost effective to produce a general purpose A/Dconverter which could be used for a wide range of frequencies.

Hence, a need exists in the art for an analog to digital signalprocessor designed for use at ultra-high frequencies greater than 2 GHz.

SUMMARY OF THE INVENTION

The need in the art is addressed by the ultra-wide band general purposeanalog to digital (A/D) signal processor of the present invention. Theprocessor includes a first circuit for shifting a frequency of an inputsignal, a second circuit for processing the input signal, and a thirdcircuit for selectively bypassing the first circuit whereby the inputsignal is provided directly to the second circuit in a first mode ofoperation and to the second circuit via the first circuit in a secondmode of operation.

In the illustrative embodiment, the first circuit is a mixer with aspecific normalized mixing ratio of 0.8 to 0.9. The second circuit is asigma-delta analog-to-digital converter. The third circuit is a switchfor passing the input signal directly to the second circuit if the inputis 20 MHz to 2 GHz or for passing the input signal to the first circuitif the input is 2 GHz to 5 GHz. In the preferred embodiment, the switch,the mixer, and the sigma-delta converter are disposed on a singleapplication specific integrated circuit (ASIC) substrate.

In the illustrative embodiment, the processor further includes a rangeselector for controlling the switch, a local oscillator connected to themixer, a first filter connected between the input signal and the secondcircuit in the first mode of operation or between the first circuit andthe second circuit in the second mode of operation, a second filterconnected between the input signal and the second circuit in the secondmode of operation, a noise-canceling tuning element connected to thesigma-delta converter, and a clock connected to the sigma-deltaconverter. In the preferred embodiment, these elements are locatedexternal to the integrated circuit.

This implementation operates by taking advantage of the maximumfrequency (2 GHz) achievable by today's state of the art sigma-deltatechnology, in combination with a specific superheterodyning frequencyscheme, allowing almost spurious-free performance for the entirecomposite frequency range of interest (20 MHz to 5 GHz). Furthermore,the processor as described above does not require any internal tuning,as conventional sigma-delta converters do. Preconditioning and tunednoise canceling can be performed external to the general purposeintegrated chip. The external elements can be easily adapted to variousinput frequencies, allowing the general purpose processor to be used asan AID converter in a variety to applications.

BRIEF DESCRIPTION OF THE DRAWINGS

The FIGURE is a block diagram of an ultra-wide band analog to digitalsignal processor constructed in accordance with the teachings of thepresent invention.

DESCRIPTION OF THE INVENTION

Illustrative embodiments and exemplary applications will now bedescribed with reference to the accompanying drawings to disclose theadvantageous teachings of the present invention.

While the present invention is described herein with reference toillustrative embodiments for particular applications, it should beunderstood that the invention is not limited thereto. Those havingordinary skill in the art and access to the teachings provided hereinwill recognize additional modifications, applications, and embodimentswithin the scope thereof and additional fields in which the presentinvention would be of significant utility.

The figure is a block diagram of an ultra-wide band analog to digital(A/D) signal processor 200 constructed in accordance with the teachingsof the present invention. The processor includes a switch 10 forcoupling the input signal to a sigma-delta analog to digital converter14 in a normal mode of operation, or to a mixer 12 in a superheterodynemode of operation. The output of the mixer 12 is input to thesigma-delta analog to digital converter 14. In the preferred embodiment,the switch 10, the mixer 12, and the sigma-delta analog to digitalconverter 14 are disposed on a single application specific integratedcircuit (ASIC) substrate 100.

Those skilled in the art will appreciate that the switch 10 is notlimited to this configuration. For instance, it can be placed at theoutput of the mixer 12, without departing from the scope of the presentteachings.

The A/D converter 200 further includes a range selector 24 forcontrolling the switch 10, a filter 20 connected between the sigma-deltaconverter 14 and the output of the switch 10 in the normal mode or theoutput of the mixer 12 in the superheterodyne mode, a noise-cancelingtuning element 22 connected to the sigma-delta converter 14, a clock 30connected to the sigma-delta converter 14, a second filter 26 connectedbetween the output of the switch 10 in the superheterodyne mode and themixer 12, and a local oscillator (LO) 28 connected to the mixer 12. Inthe preferred embodiment, these elements are located external to theintegrated circuit 100.

This implementation operates by taking advantage of the maximumfrequency (2 GHz) achievable by today's state of the art sigma-deltatechnology, in combination with a specific superheterodyning frequencyscheme, allowing almost spurious-free performance for the entirefrequency range of interest (20 MHz to 5 GHz). Furthermore, theprocessor as described above does not require any internal tuning, asconventional sigma-delta converters do. Preconditioning and tuned noisecanceling can be performed external to the general purpose integratedchip 100. The external elements can be easily adapted to various inputfrequencies, allowing the general purpose processor 100 to be used as anA/D converter in a variety of applications.

An analog RF signal is input to the integrated circuit 100 at a pin Aconnected to the switch 10. The switch 10 determines which of twopossible modes of operation the circuit is in: 1) normal, forfrequencies from 20 MHz to 2 GHz; or 2) superheterodyne, for frequenciesfrom 2 GHz to 5 GHz.

The switch 10 is controlled by an external range selector 24 which isconnected to the circuit by a pin F. The range selector can beimplemented automatically (for instance, using a high-pass filter),manually, or with a jumper.

In the normal mode of operation, the input signal is between 20 MHz and2 GHz, which can be processed by an up to 2 GHz general purposesigma-delta converter.

The input signal from pin A passes through the switch 10, and is outputthrough a pin B to an external filter 20 for preconditioning. The filter20 is a fixed filter which corresponds with the frequency of the inputsignal.

The filtered signal is re-input to the integrated circuit 100 at a pinC, and applied to an up to 2 GHz general purpose sigma-delta analog todigital converter 14. Sigma-delta A/D converters are well known in theart. A sigma-delta A/D converter includes a sigma-delta modulator and adigital filter, and operates by oversampling the signal at several timesthe Nyquist frequency. As is known in the art, sigma-delta A/Dconverters require a frequency specific noise-canceling tuning element.Accordingly, a noise-canceling filter 22 is applied externally to theintegrated circuit at a pin D and is chosen in accordance with thefrequency of the input signal. The sigma-delta A/D converter 14 alsorequires a clock 30, which is supplied externally at a pin K.

Digital data is output from the sigma-delta A/D converter 14 at a pin E.The output signal is 1-bit serial digital data, which can then heconverted to parallel digital words by a demultiplexer (DMUX).

In the superheterodyne mode of operation, additional coverage from 2 GHzto 5 GHz is provided by channeling the input signal into a specificsuperheterodyne processor with an intermediate frequency (IF) of 500MHz±70 MHz. This unique frequency scheme was chosen because it allowsspurious-free performance due to the normalized mixing ratio range of0.8 to 0.9. This provides a very clean mixer output response for any RFinput ranging from 2 GHz to 5 GHz.

When the circuit is in the superheterodyne mode, the input signal frompin A passes through the switch 10, and is output at a pin G to anexternal filter 26. The external filter 26 is a fixed filter chosen tocorrespond with the frequency of the input signal. The filtered signalis re-input to the integrated circuit 100 at a pin H, and applied to amixer 12. A local oscillator (LO) 28 is applied to the mixer 12 at a pinJ. The local oscillator 28 is chosen such that the output of the mixer12 is at an intermediate frequency (IF) of 500 MHz±70 MHz.

Those skilled in the art will appreciate that this invention is notlimited to this particular frequency scheme. For example, the mixercould also be used to up convert a signal to a frequency which could beprocessed by the sigma-delta converter.

The output of the mixer 12 is then output at pin B to an external filter20. When operating in the superheterodyne mode, the external filter 20should be an intermediate frequency (IF) filter ranging from 430 MHz to570 MHz.

The filtered signal is re-input to the integrated circuit 100 at pin C,and applied to the sigma-delta analog to digital converter 14. Anoise-canceling filter 22 is applied externally to the integratedcircuit at pin D, and is chosen to correspond with the intermediatefrequency. The sigma-delta A/D converter also requires a clock 30, whichis supplied externally at pin K.

Digital data is output from the sigma-delta A/D converter 14 at a pin E.The output signal is 1-bit serial digital data, which is usually thenconverted to parallel digital words by a demultiplexer (DMUX).

Thus, the general purpose integrated circuit 100 can be used as ananalog to digital converter for a variety of applications withfrequencies ranging from 20 MHz to 5 GHz, by applying the appropriateexternal components. The invention takes advantage of the dual modedescribed to provide for continuous operation seamnlessly from one endof the range to the other.

Thus, the present invention has been described herein with reference toa particular embodiment for a particular application. Those havingordinary skill in the all and access to the present teachings willrecognize additional modifications, applications and embodiments withinthe scope thereof.

It is therefore intended by the appended claims to cover any and allsuch applications, modifications and embodiments within the scope of thepresent invention. Accordingly,

What is claimed is:
 1. A wide band signal processor comprising: first means for shifting a frequency of an input signal; second means for processing said input signal; and third means for selectively bypassing said first means whereby said input signal is provided directly to said second means in a first mode of operation and to said second means via said first means in a second mode of operation.
 2. The invention of claim 1 wherein said first means is a down converter.
 3. The invention of claim 2 wherein said down converter is a mixer.
 4. The invention of claim 3 wherein said mixer has a normalized mixing ratio of 0.8 to 0.9.
 5. The invention of claim 1 wherein said first means is an Lip converter.
 6. The invention of claim 1 wherein said second means is a sigma-delta analog-to-digital converter.
 7. The invention of claim 1 wherein said third means is a switch.
 8. The invention of claim 7 wherein said switch is a single pole, double throw switch.
 9. The invention of claim 8 wherein said pole is connected to an input terminal, a first throw is connected to said first means and a second throw is connected to said second means.
 10. The invention of claim 8 wherein said pole is connected to said second means, a first throw is connected to an input terminal and a second throw is connected to said first means.
 11. The invention of claim 7 wherein said switch is driven by a range selector.
 12. The invention of claim 1 wherein said processor further includes a first filter connected between said input signal and said second means in said first mode of operation or between said first means and said second means in said second mode of operation.
 13. The invention of claim 1 wherein said processor further includes a second filter connected between said input signal and said second means in said second mode of operation.
 14. The invention of claim 1 wherein said processor further includes a noise-canceling tuning element connected to said second means.
 15. The invention of claim 1 wherein said processor further includes a local oscillator connected to said first means.
 16. A wide band signal processor comprising: a first circuit for shifting a frequency of an input signal; a second circuit for processing said input signal; and a third circuit for selectively bypassing said first circuit whereby said input signal is provided directly to said second circuit in a first mode of operation and to said second circuit via said first circuit in a second mode of operation.
 17. A method for processing a wide band signal including the steps of: shifting a frequency of an input signal; processing said input signal; and selectively bypassing said frequency shifting step whereby said input signal is provided directly to said processing step in a first mode of operation and to said processing step after said frequency shifting step in a second mode of operation. 